Document Type : Original Article
Authors
1 Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran
2 Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
3 Computer Network, University Putra Malaysia (UPM)
Abstract
Moore and Shannon introduced a probabilistic model in which network nodes are assumed to be completely reliable, and communication links or edges can fail with a given probability, such as p. The main problem is determining the probability that the network will remain connected under these conditions, meaning establishing a route between the source and destination terminals. If all links are operational with the same probability of p, the reliability of the entire network is described as a function of p, leading to the reliability polynomial of the network. Moore and Shannon proposed their reliability analysis on specific networks known as hammock networks. Such networks can be well adapted to array-based circuits such as FinFET, VSFET, MOSFET, NEMS, and CNFETs. In this article, focusing on hammock networks, we utilize their combination to design and implement MOS-based transistors, i.e., nMOS and pMOS, and implement basic logical gates based on such networks. To determine the reliability polynomial coefficients, various methods have been presented, most of which exhibit computational complexity due to the recursive property. In practice, for circuits with large orders and sizes, the exact calculation of reliability polynomial coefficients falls into the NP-hard complexity class. In this study, while reviewing the existing problems, efficient methods have been employed to determine the polynomial coefficients of reliability. To ensure fair and accurate comparisons and evaluations, simulation results are utilized to extract performance and reliability measures for all circuits. The reliability of the investigated networks is then compared and analyzed.
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